DOS ain't dead

Hi,
does someone know how to make a timeout in a loop executing during interrupt disabled (CLI)? Timeout would be about 1sec but it shouldn't be dependent on CPU speed. I cannot use clock/uclock/delay functions when interrupt disabled. It should also work under win9x.

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DOS gives me freedom to unlimited HW access.

> Hi,
> does someone know how to make a timeout in a loop executing during
> interrupt disabled (CLI)?

Hey, you're in a DOS board! We know everything!

> Timeout would be about 1sec but it shouldn't be
> dependent on CPU speed. I cannot use clock/uclock/delay functions when
> interrupt disabled. It should also work under win9x.

I guess that "Timeout" means that you want to wait for a certain amount of time. With interrupts disabled this can be done by scanning the "keyboard controller port B control register" (port 0061h), bit 4, which toggles with each "refresh cycle".

If this doesn't work in Win9x, you can also consider to read the PIT timer values directly (ports 40h-43h), since it counts down with a fix frequency.

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MS-DOS forever!

Thanks for suggestions!

> Hey, you're in a DOS board! We know everything!

I guess this is more releated to DOS/PCHW than DJGPP so I tried to post it here instead DJGPP group and belive here are smart guys

The KBC port - what did you mean by "refresh cycle"? Is it DRAM refresh period? I think this can vary for different DRAM chips. There are some with extended refresh time, standard is about 15us? I don't need any precise timing here but it shouldn't lock longer than 1 second if there's no response from IDE port.

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DOS gives me freedom to unlimited HW access.

> The KBC port - what did you mean by "refresh cycle"? Is it DRAM refresh
> period? I think this can vary for different DRAM chips. There are some
> with extended refresh time, standard is about 15us? I don't need any
> precise timing here but it shouldn't lock longer than 1 second if there's
> no response from IDE port.

IIRC this bit is toggled when PIT timer 1 reaches zero. PIT timer 1 was used for DRAM refresh in the original IBM PC. What's important is that the timer ticks with a known frequency and its initial counter value isn't changed usually.

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MS-DOS forever!

> The KBC port - what did you mean by "refresh cycle"? Is it DRAM refresh
> period? I think this can vary for different DRAM chips.

Don't worry, it's very old 'legacy' stuff, meaning actual DRAM refresh is done thru totally different channels, you can use the PIT channel as suggested by Japheth without any fear.

Another - easy - suggestion for your original timing question, since you don't need high precision, you may check the seconds count in "CMOS" SRAM registers.

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Ninho

> used for DRAM refresh in the original IBM PC. What's important is that the
> timer ticks with a known frequency and its initial counter value isn't
> changed usually.

And what is the channel 1 frequency? Is is 1193182 Hz? Or do I need to read some pescaler registers to determine actual frequency?

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DOS gives me freedom to unlimited HW access.