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AHCICD.SYS alternatives? (Users)

posted by RayeR Homepage, CZ, 20.01.2021, 15:40
(edited by RayeR on 20.01.2021, 16:05)

Thanks, here I post the log from my Dell work laptop - so it should have IDP and no modded driver needed:


no IDE Busmaster device (class=0x01018x) found
no SATA IDE device (class=0x010600) found
SATA AHCI device (class=0x010601) found at bus/device/function=0/23/0:
  vendor=0x8086, device=0xa102
  CMD=0x7 ([0]=IOSE,[1]=MSE (Memory Space Enable),[2]=BME (Bus Master Enable)
  EROM=0x0
  capabilities ID=0x5, next pointer=0x70
  capabilities ID=0x1, next pointer=0xa8
  capabilities ID=0x12, next pointer=0x0
  SATA capability register set found, Index-Data Pair (IDP) available
  interrupt line=11
  AHCI Base Address=0xed353000
  CAP - HBA Capabilities (RO): 0xef34ff41
  CAP.NP[0-4]=1 (# of Ports-1)
  CAP.NCS[8-12]=31 (# of Command Slots-1)
  CAP.PMD[15]=1 (1=supports multiple DRQ block data transfers for PIO)
  CAP.SAM[18]=1 (1=supports AHCI mode only)
  CAP.ISS[20-23]=3 (Interface Speed Support, 1=1.5Gb,2=3Gb,...)
  CAP.SCLO[24]=1 (1=supports Command List Override)
  CAP.SNCQ[30]=1 (1=supports Native Command Queuing)
  CAP.S64A[31]=1 (1=supports 64-bit Addressing)
  GHC - Global HBA Control: 0x80000000
  GHC.AE[31]=1 (1=AHCI Enable)
  IS - Interrupt Status Register: 0x0
  PI - Ports Implemented: 0x5 (is a DWORD bit-string, max. ports=32)
  VS - AHCI Version: 1.31
  Port 0, Base=0xed353100
    CLB - Command List Base Address=0x9d800
    FB - FIS Base Address=0x9dc00
    IS - Interrupt Status=0x0 ([0]=D2H Reg FIS, [1]=PIO Setup FIS, [2]=DMA Setup FIS, ...)
    IE - Interrupt Enable=0x0
    CMD - Command and Status=0x4004016
    CMD.FRE[4]=1 (1=FISes may be written to FIS receive area)
    CMD.CCS[8-12]=0 (Current Command Slot)
    CMD.FR[14]=1 (1=FIS receive running)
    CMD.CR[15]=0 (1=Command List running)
    CMD.HPCP[18]=0 (1=Hot Plug Capable Port)
    CMD.ATAPI[24]=0 (1=device is ATAPI)
    TFD - Task File Data=0x50
    SIG - Signature=0x101 (received from device on first D2H register FIS)
    SSTS - SATA Status=0x133 (Device Detection[3:0]=3, Interface Speed[7:4]=3, Power Management[11:8]=1)
    SCTL - SATA Control=0x300 (DET[3:0]=0, SPD[7:4]=0, IPM[11:8]=3)
    SERR - SATA Error=0x0
    SACT - SATA Active=0x0 (bit string for max. 32 command slots)
    CI - Command Issued=0x0 (bit string for max. 32 command slots)
      CL Base=0x9d800, size=0x400 (32*32)
      CL[0] PRDTL=1 CFL=5 flgs+PMP=0x0 PRDBC=0x200 (PRDTL=items in PRDT)
      CL[0] Command Table Base Address=0x9dd00 (CFIS=+0 ACMD=+0x40 PRDT=+0x80)
        CFIS: type=0x27
        PRDT: 0x9be00 0x1ff
      (received) FIS at 0x9dc00, size=0x100 (DSFIS=+0 PSFIS=+0x20 RFIS=+0x40 UFIS=+0x60)
  Port 2, Base=0xed353200
    CLB - Command List Base Address=0x9d800
    FB - FIS Base Address=0x9dc00
    IS - Interrupt Status=0x0 ([0]=D2H Reg FIS, [1]=PIO Setup FIS, [2]=DMA Setup FIS, ...)
    IE - Interrupt Enable=0x0
    CMD - Command and Status=0x4004016
    CMD.FRE[4]=1 (1=FISes may be written to FIS receive area)
    CMD.CCS[8-12]=0 (Current Command Slot)
    CMD.FR[14]=1 (1=FIS receive running)
    CMD.CR[15]=0 (1=Command List running)
    CMD.HPCP[18]=0 (1=Hot Plug Capable Port)
    CMD.ATAPI[24]=0 (1=device is ATAPI)
    TFD - Task File Data=0x7f
    SIG - Signature=0xffffffff (received from device on first D2H register FIS)
    SSTS - SATA Status=0x4 (Device Detection[3:0]=4, Interface Speed[7:4]=0, Power Management[11:8]=0)
    SCTL - SATA Control=0x330 (DET[3:0]=0, SPD[7:4]=3, IPM[11:8]=3)
    SERR - SATA Error=0x0
    SACT - SATA Active=0x0 (bit string for max. 32 command slots)
    CI - Command Issued=0x0 (bit string for max. 32 command slots)


BTW how hard would sending ATA commands via AHCI compared to old PIO? When my program is already in pmode and I can map the MMIO, this is not problem in DJGPP. I didn't studied AHCI yet. Is the standard generic enough it would work then also for AMD AHCI and other manuf.?

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DOS gives me freedom to unlimited HW access.

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