Hello RayeR,
> that use pmode like JEMM, etc... If I understand well intel should have
> some control bit to switch between new and legacy behavior so there should
> not be problem until they remove that legacy mode...
Yes, that seems to be true, at least for Intel's proposal. Apparently the new stuff will only kick in for 64-bit OSes; Section 3 says
> The FRED architecture is defined for use by a 64-bit operating system.
> Except where noted, changes to processor behavior and new instructions
> apply only in IA-32e mode (if IA32_EFER.LMA = 1) and not to legacy protected
> mode (or real-address mode).
I think the general idea is that Intel wants a CPU --- when handling a page fault, invalid instruction, etc. --- to avoid having to deal with an IDT in the first place. An IDT is a data structure in memory, so processing an interrupt through an IDT means a CPU needs to read from main memory, which is slow. If instead there are a bunch of (new) special registers in the CPU which say exactly how to handle an exception, then the CPU can read them very quickly, and start running the exception handler in no time.
I have not looked yet at what AMD is proposing, but it is reportedly less radical than Intel's, so I would guess it is also meant to be backward-compatible.
Thank you! ---
https://gitlab.com/tkchia · https://codeberg.org/tkchia · 😴 "MOV AX,0D500H+CMOS_REG_D+NMI" |
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