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Turbo C - ISR chaining? (Developers)

posted by RayeR , CZ, 05.12.2020, 00:26

Hi, is there some helper function/macro in Borland BC/TC for chaining ISR (DJGPP has such feature)? I'd like to hook and let my ISR code be called first, without modifying registers and when done call the old ISR with original registers. Problem is that BC automatically saves and restores all registers in ISR in its prolog/epilog code and when i do
ISR()
{
mycode;
oldisr();
}
then oldisr gets changed registers by my code and registers that oldisr sets are vanished by epilog code that restores all, so I'd need to call it in order
ISR()
{ // epilog save regs
mycode;
} // epilog restore regs
oldisr(); // call old ISR with original regs

I prefer to do as much as possible in C and avoid ASM but if BC/TC have any helper I'll have to do ASM. BTW can BC/TC do naked function?

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DOS gives me freedom to unlimited HW access.

Complete thread:

• Turbo C - ISR chaining? - RayeR, 05.12.2020, 00:26 (Developers)
  • Turbo C - ISR chaining? - tkchia, 05.12.2020, 07:09
    • Turbo C - ISR chaining? - RayeR, 06.12.2020, 18:25
  • Turbo C - ISR chaining? - alexfru, 05.12.2020, 09:48
    • Turbo C - ISR chaining? - RayeR, 06.12.2020, 18:29
      • Turbo C - ISR chaining? - alexfru, 07.12.2020, 06:32
        • Turbo C - ISR chaining? - tom, 07.12.2020, 14:42