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more insight into BIOS MTRRs (Users)

posted by Laaca Homepage, Czech republic, 23.03.2011, 23:25

> I don't know anything about PAT yet, have some good docs?
> Maybe it's way to solve core i3/5/7 issue.

Hm.. Maybe.
I found this snippet from discussion:

Liang Yang wrote:
> Hi,
 >
> It seems we can set the memory access type (WB, WC, WT etc.) by either using
> PAT or MTRR on x86 CPUs.
> My question is:
> Are PAT and MTRR always consistent with each other? If there is
> inconsistence between them, which one decides the true memory access type?

This is well documented in the Intel references, but in short, the
cache control bits in the page tables (including those indirectly
referenced via the PAT) and the caching controls in the MTRRs are
largely independent of one another. That being said, if caching
controls are set for a given location by more than once mechanism, the
most restrictive (least amount of caching) policy specified wins. Thus
if the MTRR specifies no caching but the page table specifies
cacheable, the page is uncached, the reverse scenario (MTRR::cacheable,
page:uncachable) also results in an uncachable page.

Several other rules apply, for example, if write through is specified
in one place and write back in the other, write through wins.

---
DOS-u-akbar!

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